In order to determine the state of a memory bit inside an array, it is common practice to compare the state of the array bit to the state of a pre-set reference. For example, a mid-point reference signal can be generated by averaging the signal from two reference bits, one in a high signal state, and one in a low signal state.
Memory devices commonly include some form of error correcting code (ECC) in the output logic circuitry. If a memory bit is disturbed from its desired state, or is otherwise read incorrectly, the ECC may be used to discover and possibly correct the memory output. It is not uncommon for reference bits to be disturbed (i.e., changed to an incorrect state) during processing, packaging, and/or at any other time. If a reference bit is disturbed from its original state, the memory bits compared to that reference bit may be subject to an unusually large number of read errors.
Prior art memory systems are incapable of efficiently recovering from the presence of one or more disturbed reference bits. Accordingly, most efforts have been centered on making memory devices more robust, i.e., lowering the rate which reference bit disturbs occurs.
The potential for an external field to manipulate MRAM data is a concern for applications with critical and/or secure data. For many of these applications, it is essential that they detect when the data has been disturbed; however, not necessary that the data be recoverable. A secondary concern is that a sufficiently strong external field will render the MRAM permanently non-functional. Two common fail modes resulting from a high external field, both of which cause a remnant elevated fail rate, are cladded line disturbs and reference bit disturbs. It would be desirable to recover functionality after the occurrence of either of those events.
The occurrence of a double bit failure in an ECC word is of sufficiently low probability that it is a good indicator that the accessed ECC word has been tampered with. However, monitoring a single word may not be sufficient since there will be a wide range of susceptibility across the device and other words can accumulate double bit fails while the monitored word remains correct. In addition, the known double bit error detection scheme is not guaranteed to detect all fails in excess of two (but, will usually detect any even number of fails). It may be possible when monitoring a single ECC word that an extreme disturb condition caused an undetectable number of fails. By monitoring a range of ECC words, the probability of detecting the first signs of tampering, as well as extreme disturbs, is increased.
Accordingly, there is a need for a memory device (e.g., a MRAM memory device) incorporating self-healing reference bit methods. Furthermore, other desirable features and characteristics of the exemplary embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.